Parallel Distributed Infrastructure for Minimization of Energy

TEASE: A Systematic Analysis Framework for Early Evaluation of FinFET-based Advanced Technology Nodes

Publication Type:

Conference Paper

Source:

Proceedings of the 50th Annual Design Automation Conference, ACM, New York, NY, USA, p.24:1–24:6 (2013)

ISBN:

978-1-4503-2071-9

URL:

http://doi.acm.org/10.1145/2463209.2488764

Keywords:

FinFET technology, SoC evaluation, standard cell architecture